ECS 243 CODE GENERATION AND OPTIMIZATION
(4) II
Lecture: 3 hours
Discussion: 1 hour
Prerequisite: Course 201A or Engineering Electrical and Computer 270
Grading: Letter; problem sets (10%), project (30%), midterm (20%), final (40%)
Catalog Description:
Compiler optimizations for performance, code size and power reduction. Topics include control- and data-flow analysis, redundancy elimination, loop and cache optimizations, register allocation, local and global instruction scheduling, and modulo scheduling.
Expanded Course Description:
- Introduction
- Overall compiler organization: frontend, backend
- Intermediate representation: high-level, low level
- Backend organization
- Control-Flow Analysis
- Basic blocks
- Control-flow graph
- Loop invariant computations
- Dominators
- Loops
- Call graph
- Program profiling
- Control-Oriented Optimizations
- Loop-Invariant Code Motion
- Induction Variable Elimination
- Loop Unrolling
- Modulo Scheduling
- Loop Reversal, Interchange, Pealing, Fission, Fusion, Unswitching, Collapsing
- Data-Flow Analysis
- Data Dependence
- Aliasing
- Static Single Assignment
- Reaching Definitions
- Def-Use Chains, Use-Def Chains
- Bit-Vector Iterative Analysis
- Live-Range Analysis (Web Analysis)
- Symoblic-Register Renumbering, Interference
- Available Expressions
- Value Numbering
- Data-Oriented Optimizations
- Dead-Code Elimination
- Copy propagation
- Cod Hoisting/Sinking
- Common Sub-Expression Elimination
- Partial Redendancy Elimination
- Strength Reduction
- Register Allocation
Textbooks: K.Cooper and L. Torczon, Engineering A Compiler (chapters 8-13), Morgan Kaufmann, 2003. Plus papers from the literature.
Instructor: K. Wilken
Prepared by: K. Wilken
Overlap Statement: There is no significant overlap with another course.
3/07
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