Rakesh Kumar
Department of Computer Science and Engineering
University of California, San Dieg0
Tuesday, March 14
3 :10-4:00 p.m.
1065 Kemper - refreshments to follow in 1131 Kemper Hall
Heterogeneous Multi-core Computing
We are on the cusp of a major technology shift. We are moving to an era where a single chip will likely be a massively parallel, computationally dense, and power-limited behemoth. In this talk, I will show that this technology shift provides us new, unique opportunities to address some classical problems in computer architecture, like high die-area and power.
Specifically, computation cost on current processors is high because of the inability of processors to adapt to diversity in workloads. I will present Single-ISA Heterogeneous Multi-Core Architectures. These architectures recognize the diversity in workloads and adapt to them. A heterogeneous architecture consists of cores with different power/performance characteristics on the same die. Applications are then mapped to the "best-fit" cores for efficient execution. A heterogeneous multi-core architecture can reduce the power consumption of a processor by up to six times. This is at least two times more than any other reported architectural technique, including frequency/voltage scaling and clock gating. Such a processor can also provide significantly higher throughput than other processor designs. The throughput benefits can be achieved without any loss of single-thread performance. I will also describe the scheduling policies and mechanisms that we developed to exploit the potential of these architectures. Several of these policies are applicable even to other domains, like a chip multiprocessor (CMP) of simultaneously multithreaded (SMT) cores.
Biography: Rakesh Kumar is a PhD Candidate in computer engineering at the University of California, San Diego. His research interests include computer systems and architectures that can exploit multiple levels of concurrency in workloads and can proactively adapt to different application requirements. He has also worked on low-power architectures, multiprocessor coherence, and on-chip interconnects.
Rakesh received a BS in computer science and engineering from the Indian Institute of Technology (IIT), Kharagpur. He is a recipient of the IBM PhD Fellowship and a CalRA Fellowship. He was also most recently a Program Chair of the Workshop on Design, Architecture, and Simulation of Chip Multiprocessors (dasCMP).