Computer Science

“Heterogeneous Computing and Big Data”

CS Colloquium Seminar: Emeritus Professor Uri Weiser from Technion IIT

Host: Matt Farrens

When: Friday, June 1, 2018 @ 2pm

Where: 1003 Kemper Hall

Title: “Heterogeneous Computing and Big Data”

The computing world is approaching a new era, technology-wise. Moore’s law is, at best, slowing down, the end of Dennard’s scaling limits the number of transistors on die functioning at the same time due to power limitations; power and energy have become important limiting factors.  Requirement-wise, performance needs continue to soar while new requirements and technologies are driving us towards Big Data and Machine Learning.  All these forces are driving the computing world towards new architectural potential solutions in different forms of heterogeneous computing, in which narrowing the application’s range makes it possible to reach the new requirement efficiency values (e.g. Performance/Power). The efficiency of our future system will depend on the accelerator’s performance level and the flexibility (programmability) of using the accelerators for similar applications. This two requirement axes define the accelerator’s basic efficiency.  However, Machine Learning applications have pretty narrow basic computing requirements: e.g. while executing the inference engine, there are almost no branches, while the basic operation is MAC and some nonlinear operations. Thus, at the execution level the solution space is becoming more defined.

In this talk, we will present the current basics/basic environment and try to convey some insights related to Big Data and Machine Learning implementation.

Uri Weiser – bio
Uri Weiser is a professor emeritus in the Electrical Engineering department of the Technion IIT and is involved in numerous startups.  He received his bachelor’s and master’s degrees in EE from the Technion and his Ph.D in CS from the University of Utah, Salt Lake City. Professor Weiser worked at Intel from 1988 till 2007. At Intel, Weiser initiated the definition of the Pentium® processor; drove the definition of Intel’s MMX™ technology, invented the Trace Cache, co-managed a new Intel Microprocessor Design Center in Austin Texas, and formed an Advanced Media applications research activity.  Weiser was appointed as an Intel Fellow in 1996. In 2002, he became an IEEE Fellow; in 2005, an ACM Fellow; and in 2016, he was awarded the prestigious Eckert Mauchly award.

Prior to his career at Intel, Professor Weiser worked for the Israeli Department of Defense as a research and systems engineer, and later, for National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.

1003 Kemper Hall

Loading Map....