X-Sender: trivu@katamail.com@pop.katamail.com Date: Wed, 06 Aug 2003 18:05:13 +0200 To: bai@cs.ucdavis.edu From: Triverio Subject: Test data for model order reduction Mime-Version: 1.0 X-Spam-Status: No, hits=0.0 required=5.0 tests=none version=2.55 X-Spam-Checker-Version: SpamAssassin 2.55 (1.174.2.19-2003-05-19-exp) X-Keywords: Good morning, I'm an electronic engineer who just received the laurea from the Politecnico di Torino, Italy. I realized a thesis on model order reduction techniques and I read your article "Krylov subspace techniques for reduced-order modeling of large scale dynamical systems" published on "Applied numerical mathematics". If you are interested, I can send you some benchmark models for your website. They are related to a binary tree of transmission lines. A structure like this can approximately model an electronic interconnection network (e.g. the clock distribution system of an integrated circuit). Each transmission line is modeled as a sequence of RLC blocks. I attached to the email an example. The matrices are related to the equations G x + C dx/dt = B u y = L' x The system has dimension 2530, 9 ports, 1672 states. If you need more details about this model or systems with a different dimension or more ports write to me. The binary tree is fully parametrized. I can also generate a SPICE compatible subcircuit of the tree. I also found a lot of free, interisting various models for order reduction at http://www.win.tue.nl/niconet/NIC2/benchmodred.html Best regards, Piero Triverio (triverio@tin.it) Electronic engineer Politecnico di Torino, Italy Home address: via Tomati 41/A, 13811 Tavigliano (BI), ITALY Tel. +39-015-471129