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\begin{document}

\title{Appendix B:  DLX}

\author{Norman Matloff \\
University of California at Davis}                                

\date{October 30, 1996}

\maketitle            

\section{}

The DLX has 32-bit words and 32-bit addresses.  It features 32-bit
words and addresses, and includes 32 general-purpose registers r0-r31,
and 32 floating-point registers f0-f31. 

Following is a partial list of the DLX instruction set.  In it ``sr''
(or ``sr1'' and ``sr2''), ``dr'' and ``c'' stand for ``source
register,'' ``destination register'' and ``constant,'' and are of sizes
5 bits, 5 bits and 16 bits, respectively; m[z] refers to the contents of
memory location z.  Also, ``u5'' means an unused 5-bit field.  A long
(26-bit) constant is denoted by ``lc''.

\begin{verbatim}
assemb. syntax     machine language                  action
--------------     ----------------                  ------

lw dr,c(sr)        100011 sr dr c                    dr <-- m[c+sr]
lh dr,c(sr)        100001 sr dr c                    dr <-- m[c+sr] (halfword)
lb dr,c(sr)        100000 sr dr c                    dr <-- m[c+sr] (byte)
lhi dr,c           001111 u5 dr c                    dr <-- c concat 0x0000
sw c(sr),dr        101011 sr dr c                    m[c+sr] <-- dr
sb c(sr),dr        101000 sr dr c                    m[c+sr] <-- dr (byte)

add dr,sr1,sr2     000000 sr1 sr2 dr u5 100000       dr <-- sr1 + sr2
sub dr,sr1,sr2     000000 sr1 sr2 dr u5 100010       dr <-- sr1 - sr2
addi dr,sr,c       001000 sr1 dr c                   dr <-- sr + c
subi dr,sr,c       001010 sr1 dr c                   dr <-- sr - c

and dr,sr1,sr2     000000 sr1 sr2 dr u5 100100       dr <-- sr1 & sr2
or dr,sr1,sr2      000000 sr1 sr2 dr u5 100101       dr <-- sr1 | sr2
xor dr,sr1,sr2     000000 sr1 sr2 dr u5 100110       dr <-- sr1 xor sr2
andi dr,sr,c       001100 sr1 dr c                   dr <-- sr & c
ori dr,sr,c        001101 sr1 dr c                   dr <-- sr | c
xori dr,sr,c       001110 sr1 dr c                   dr <-- sr xor c
sra dr,sr1,sr2     000000 sr1 sr2 dr u5 000111       dr <-- sr1 >> sr2 (arith)
srai dr,sr,c       010111 sr dr c                    dr <-- sr1 >> c (arith)
srl dr,sr1,sr2     000000 sr1 sr2 dr u5 000110       dr <-- sr1 >> sr2 (logical)
srli dr,sr,c       010110 sr dr c                    dr <-- sr1 >> c (logical)
sll dr,sr1,sr2     000000 sr1 sr2 dr u5 000100       dr <-- sr1 << sr2 (logical)
slli dr,sr,c       010100 sr dr c                    dr <-- sr1 << c (logical)

slt dr,sr1,sr2     000000 sr1 sr2 dr u5 101010       dr <-- (sr1 < sr2)
slti dr,sr,c       011010 sr dr c                    dr <-- (sr < c)
sle dr,sr1,sr2     000000 sr1 sr2 dr u5 101100       dr <-- (sr1 <= sr2)
slei dr,sr,c       011100 sr1 sr2 dr c               dr <-- (sr <= c)
seq dr,sr1,sr2     000000 sr1 sr2 dr u5 101000       dr <-- (sr1 == sr2)
seqi dr,sr,c       011000 sr1 sr2 dr c               dr <-- (sr == c)
sge dr,sr1,sr2     000000 sr1 sr2 dr u5 101101       dr <-- (sr1 >= sr2)
sgei dr,sr,c       011101 sr1 sr2 dr c               dr <-- (sr >= c)
sgt dr,sr1,sr2     000000 sr1 sr2 dr u5 101011       dr <-- (sr1 > sr2)
sgti dr,sr,c       011011 sr1 sr2 dr c               dr <-- (sr > c)
sne dr,sr1,sr2     000000 sr1 sr2 dr u5 101000       dr <-- (sr1 != sr2)
snei dr,sr,c       011001 sr1 sr2 dr c               dr <-- (sr != c)
beqz sr,c          000100 sr u5 c                    if (sr == 0) pc <-- pc + c
bnez sr,c          000101 sr u5 c                    if (sr != 0) pc <-- pc + c
j lc               000010 lc                         pc <-- pc + lc
jal lc             000011 lc                         r31 <-- pc+4; pc <-- pc + lc; 
jalr sr            010011 sr u21                     r31 <-- pc+4; pc <-- sr; 
jr sr              010010 sr u21                     pc <-- sr; 

nop                0x00000000                        do nothing
\end{verbatim}

\section{Simulator}

\subsection{Overview}

DLX was originally an example in the computer architecture
text, {\it Computer Architecture:  A Quantitative Approach} (Morgan
Kaufman), by David Patterson at UC Berkeley and John Hennessy at
Stanford University.  Their use of DLX is mainly as a vehicle for
studying which features of an architecture are (a) frequently used
in common applications and (b) implementable as a speedy machine.

You can obtain the DLX source code, and much other material, from
the DLX home page:

\begin{verbatim}
http://Literary.COM//mkp/new/hp2e/hp2e_resources0.html#dlx
\end{verbatim}

The package includes not only the simulator itself, {\bf dlxsim}, but
also a DLX configuration of the GNU C compiler {\bf gcc}, called {\bf
dlxcc}.  The latter is an extremely valuable feature, allowing you to
write C programs to run on DLX.

There is, however, no separate assembler.  Instead, the simulator
itself does the assembly.  Programs are input to the simulator as
files with the .s suffix (standard for assembly language files on
Unix systems).  Such files are produced either directly, via a text
editor, or indirectly by running {\bf dlxcc} on a C-language source
file.

\subsection{Installation}

The overall source package is quite large, and at some point during the
compilation process you will need more than 20 megabytes of disk
space.\footnote{However, binary executables for {\bf dlxsim} and {\bf
dlxcc} are small, about 0.4 megabyte total.  If you know someone who has
these files, you may wish to use those directly.} Compile the simulator
according to the instructions.  Finally, make sure to place {\bf dlxsim}
and {\bf dlxcc} somewhere in your search Unix path.

\subsection{Compiler Operation}

For example, suppose you have prepared a C-language source file named
gy.c.  Simply type

\begin{verbatim}
dlxcc gy.c
\end{verbatim}

and a file gy.s, consisting of DLX assembly language, will be
produced.\footnote{That file will be located in the same directory
as gy.c.}  It may now be loaded and run under {\bf dlxsim}, using
the latter's {\bf load} command.

\subsection{Simulator Operation}

For our purposes here, usage for the simulator is simple; just type

\begin{verbatim}
dlxsim
\end{verbatim}

Here are a few of the commands which are available in {\bf 
dlxsim}:

{\bf put:}  Set the contents of a register or memory location to a
specified value.  The address or value can be specified either in hex
form, using the 0x prefix, or decimal form (no prefix).  For example:

\begin{verbatim}
(dlxsim) put 0x104 5
\end{verbatim}

will place the value 5 into memory location 0x104.  (Use hex for
negative values.)

{\bf get:}  Check the contents of a register, a memory location, 
or a set of contiguous memory locations.  The optional second argument
specifies how many consecutive locations are to be checked, and in what
format.  For example:

\begin{verbatim}
(dlxsim) put 0x244 3
(dlxsim) put 0x248 9
(dlxsim) get 0x244 2
0x244:  0x00000003
0x248:  0x00000009
\end{verbatim}

A partial list of formats available are:

\begin{verbatim}
c   interpret as ASCII characters
d   decimal
i   interpret as DLX instructions, and disassemble them
x   hex (default)
\end{verbatim}

{\bf load:}  Load the indicated .s files, beginning at location 0x100.
If the .s code came originally from .c source, 0x100 will be named
\_main.  Note:  If multiple files are to be ``linked'' into one
executable, they must be loaded simultaneously, as in

\begin{verbatim}
(dlxsim) load a.s b.s
\end{verbatim}

{\bf step:}  Execute a single instruction, the one pointed to by the
pc register.  In what appears to be a bug, though, the very first
time you use this command for a program run, you must indicate the
initial value of the pc register; after the first invocation of
the {\bf step} command with an address, you need not specify the
address from that point on.  For example:

\begin{verbatim}
(dlxsim) load c.s
(dlxsim) get 0x100 12i
_main:  add r14,r0,r0
_main+0x4:      lhi r14,0x0
_main+0x8:      addui r14,r14,0xfffc
_main+0xc:      sw 0xfffc(r14),r30
_main+0x10:     sw 0xfff8(r14),r31
_main+0x14:     add r30,r0,r14
_main+0x18:     addi r14,r14,0xffd0
_main+0x1c:     sw 0x0(r14),r3
_main+0x20:     sw 0x4(r14),r4
_main+0x24:     sw 0x8(r14),r5
_main+0x28:     addi r5,r0,0x2
_main+0x2c:     sw 0xfff4(r30),r5
(dlxsim) step 0x100
stopped after single step, pc = _main+0x4: lhi r14,0x0
(dlxsim) step
stopped after single step, pc = _main+0x8: addui r14,r14,0xfffc
\end{verbatim}

{\bf go:}  Execute the code, starting with the one pointed to by the
pc register, continuing until a breakpoint is reached.

{\bf stop at:}  Specify a breakpoint, to be used in conjunction
with the {\bf go} command.  For example:

\begin{verbatim}
(dlxsim) stop at 0x12c
\end{verbatim}

{\bf asm:}  Assemble the argument, and report the resulting
machine code.  For instance:

\begin{verbatim}
(dlxsim) asm "add r1,r4,r9"
0x890820
\end{verbatim}

Note that the quotation marks are mandatory.

{\bf quit:}  Exit the simulator. 

\end{document} 

